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Burst-Mode PON Controller
With Integrated Monitoring
Table 02h, Register 89h: Config
FACTORY DEFAULT
READ ACCESS
WRITE ACCESS
MEMORY TYPE
00h
PW2
PW2
Nonvolatile (SEE)
89h
FETG DIR
TX-F EN
RESERVED
ASEL
RESERVED
RESERVED
RESERVED
RESERVED
bit7
Configure the memory location and the polarity of the digital outputs.
FETG DIR: Chooses the direction or polarity of the FETG output for normal operation.
bit0
bit7
bit6
bit5
bit4
bit3:0
0 = Under normal operation, FETG will be pulled low. (Default)
1 = Under normal operation, FETG will be pulled high.
TX-F EN:
0 = The alarm bits will immediately reflect the status of the last comparison. (Default)
1 = The alarm bits are latched until cleared by a TX-D transition or Power-down. If V CC low alarm is
enabled for either FETG or TX-F then latching is disabled until after the first V CC measurement is
made above the V CC to set-point to allow for proper operation during slow power-on cycles.
RESERVED
ASEL: Address SELect.
0 = Device Address of A2h (Default).
1 = Device-Address is equal to the value found in byte ‘ device_address ’ (Table 02h, 8Ch).
RESERVED
Table 02h, Register 8Ah: Startup Step
FACTORY DEFAULT:
READ ACCESS
WRITE ACCESS
MEMORY TYPE:
00h
PW2
PW2
Nonvolatile (SEE)
8Ah
2 12
2 11
2 10
2 9
2 8
2 7
2 6
2 5
bit7
This value will define the maximum allowed step for the upper 8 bits of IBIAS output during start-up.
bit0
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47
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